`timescale 10ns/1ns

module signal_gen_top_tb;

  // Parameters
  parameter T = 10  ;
  parameter sim = 1 ;
  // Ports
  reg  in_clk_50m = 0;
  reg  a_adj = 1;
  reg  w_adj = 1;
  reg  duty_adj = 1;
  reg  iq_adj = 1;
  reg  f_add_adj = 1;
  reg  f_sub_adj = 1;
  wire dac_ch;
  wire dac_clk;
  wire dac_wr;
  wire [9:0] dac_d;
  wire led;
  reg  rst_n  ;
  
  
  signal_gen_top 
   #(.T(T),
     .sim (sim))
  signal_gen_top_dut (
    .rst_n      (rst_n)  ,
    .in_clk_50m (in_clk_50m ),
    .a_adj (a_adj ),
    .w_adj (w_adj ),
    .duty_adj (duty_adj ),
    .iq_adj (iq_adj ),
    .f_add_adj (f_add_adj ),
    .f_sub_adj (f_sub_adj ),
    .dac_ch (dac_ch ),
    .dac_clk (dac_clk ),
    .dac_wr (dac_wr ),
    .dac_d (dac_d ),
    .led  ( led)
  );

  initial begin
    begin
     
    rst_n = 0;
    #5 ;
    
    rst_n = 1;
        repeat (2)
        begin 
        #10000
        f_add_adj = 0 ;
        #1000 ;
        f_add_adj = 1 ;
        #100 ;    
        end 
        
    
        repeat (2)
        begin 
        #10000 ;
        f_sub_adj = 0 ;
        #1000 ;
        f_sub_adj = 1 ;
        #100 ;    
        end        
		  
    repeat (1)
        begin 
        #10000 ;
        w_adj = 0 ;
        #1000 ;
        w_adj = 1 ;
        #100 ;    
        end 
		  
	 repeat (2)
        begin 
        #10000
        f_add_adj = 0 ;
        #1000 ;
        f_add_adj = 1 ;
        #100 ;    
        end 
		  
   repeat (2)
        begin 
        #10000 ;
        f_sub_adj = 0 ;
        #1000 ;
        f_sub_adj = 1 ;
        #100 ;    
        end        
		  
	 repeat (2)
        begin 
        #10000 ;
        w_adj = 0 ;
        #1000 ;
        w_adj = 1 ;
        #100 ;    
        end 	  
		  
    repeat (9)
        begin 
        #10000 ;
        duty_adj = 0 ;
        #100 ;
        duty_adj = 1 ;
        #100 ;    
        end 

    end
  end

  always
    #1  in_clk_50m = ! in_clk_50m ;

endmodule
